1. Field of the Invention
The present invention relates to data drivers, and more particularly, to a digital data driver and a liquid crystal display using the same.
2. Description of the Related Art
Conventionally, digital drivers of active matrix liquid crystal display (AMLCD) use storage registers (digital latches) as line buffers to store the digital video signal in line time and to drive the Digital to Analog Converter (DAC) in a line-at-a-time mode. FIGS. 1A and 1B show the architecture of a conventional 6-bit digital data driver operating in line-at-a-time mode. According to this kind of architecture, the digital video data signals R[5]˜B[0] are loaded into the first level corresponding latches (Latch11) by the enable signal from the shift register SRn during each horizontal scanning period. Thereafter, all video signals R[5]˜B[0] stored in the first level latches (Latch11) are written to the second level latches (Latch12), and input to the DACs (DAC-Rn, DAC-Gn and DAC-Bn) simultaneously by the signal LB. According to the enable signal from the next shift register SRn+1, the digital video data signals R[5]˜B[0] on the data lines at present are loaded into the first level corresponding latches (Latch21). Next, all video signals R[5]˜B[0] stored in the first level latches (Latch21) are written to the second level latches (Latch22), and input to the DACs(DAC-Rn+1, DAC-Gn+1 and DAC-Bn+1) simultaneously by the signal LB. As resolution of AMLCD is increased the bit numbers of the data also increases such that the numbers of the digital data driver occupy a larger layout area. In the conventional arrangement, however, the high resolution AMLCD suffers from the limited lateral layout area in the digital data driver. Thus, when the resolution of the AMLCD is increased, layout difficulty in wire routing caused by additional latches and DACs.